ENGINEERING AND SYSTEM ASPECT OF COMPUTER DESIGN (Part Two)

Originally Published in 1992 (Computer Jagat Magazine)

Hakikur Rahman

Two type of MOSFETs are available; p-channel and n-channel. Each of them consists of a drain, a source, a gate and a substrate area with external terminals, p-channel MOSFETs are applied with negative voltage at the gate and positive voltage to n-channel. Hence, they act as switch and used in relay contact (voltage applied to gate, drain to source resistance varies and a connection or disconnection happens there).

Main advantage of CMOS is its extremely low power dissipation, due to current sensitivity and relatively high speed of operation (in order of 25 MHz of operation or more). CMOS NAND and NOR gate are practically available.

Usually, Logic gates are classified according to their fan-in-factor (which is the number of inputs available to a gate), for example, fan-in : 2 means a 2-input NAND gate or, fan-in : 4 means a 4-input NOR gate, etc. Similarly, for DIL packages the number of inputs which can be fed from one output is called fan-out factor and this may varies from 5 to 10, including power gates supplying up to 50 inputs. 14orl6orl8DIL packages are usually available.

Most common manufacturers, like Texas Instruments, Fujitsu or Signetics are marketing logic subsystems in integrated circuit form for their NAND/NOR elements. They can classify as MSI (Medium Scale Integration) subsystems.

MSI subsystems has few basic building blocks, which need to be clarified.

Arithmetic logic half-adder circuits are used in basic binary arith-metic systems at single or multiple gated full-adder stages as exclusively OR plus carry logic gates. Look-a-head carry generators are also provided by most of the Manu factures.

Bistable elements such as JK, SR and D-type clocked bistable circuits are found particularly in TTL systems. Some of them include master-slave (dual-latch) bistable circuits or, d.c. SR (toggles or latches) bistable circuits. These circuits are usually constructed from quad 2-input NAND/NOR packages.

Single-shot or monostable elements are used for timing control and oscillation purposes in the clock circuitry.

Counters in both synchronous and asynchronous form are used for binary, BCD and decade counting circuits as up or down counter.

Registers such as single or multiple-stage shift registers with parallel/serial input/output are normally used for storing and manipulating digital data.

Line drivers such as power amplifiers for driving peripheral devices like, relay contactors, paper tape readers, etc.

Transceivers are used in bidirectional bus driver circuits for input-output purposes.

UARTs   (Universal   Asynchronous Receiver Transmitter) for interfacing input-output peripherals such as communication channels in networks.

Analogue-to-digital converters are use for conversion of analogue signals to logic voltage level of Os and Is and vice versa.

Voltage level changer and opt isolators are used for interfacing one type of logic system to another type by changing logic voltage levels.

Decoders and comparator circuits used to multiplex a number of input channels to a single output, say memory address decoding, RAM decoding, etc., and for comparing binary numbers or parity checking purposes.

ROM and PLAs are used for decoding and table-loo-up purposes.

Expandable gates such as a DTL NAND gate to the base of transistor, used to increase fan-in factor of the element, usually called expanders. Sometime, fan-out factor can also be increased by using separate buffer amplifiers.

There are few factor also to be compared for logic systems :

Type of Logic : For high speed purposes DTL, RTL, TTL, ECL are selected, for low power circuits CMOS are prescribed.

Fan-in/Fan-out factors : This involves propagation delay, when used in conjugation with expanders.

Speed : The maximum switching rate of simple set-reset bis-tables, also known as toggle-rate, varies from 500 KHz to 150 MHz for ICs.

Propogation delay : The time delay through the element between input and output waveforms which vary with loading temperature, fan-out and collector supply voltage. Typical propogation delay ranges from 1-100 ns with average of 10 ns.

Supply voltages : To determine the supply voltage, type of logic is important, whether it is negative or positive logic; maximum terminal rating, the limiting value which can happen before any damage to the component; line voltage and tolerance, normally 10 to 20% except for ECL, which has less tolerance value; etc.

Type of package : Here size of module is important, whether it is TOS or DIL or flat-pack or surface-mounted, their pin spacing, can give information on how easy the hardware assembly would be or whether package will have any replacement problem, etc.

Chip failure rate : Simulation of failure rate is quite difficult at the manufacturing stage, since diversified data is not available at that moment.- However, using computer simulation this thing is being taken care of.

Circuit’s DC noise immunity : This is very important factor to a logic system, which is the difference of logic output and input voltage. A circuit’s noise level, also depends on other factors, such as working temperature, ambient temperature, power supply voltage and current and fan-out.

Capacitance between gates or subsystems : Always capacitance effect is kept at the minimum and circuits are manufactured to be able to run with longer cables. Usually longer cables induce higher capacitance value, which depends on the output impedance and it must be low to prevent more power dissipation, DC internal noise, etc.

Type of logic function : This is the most important factor, whether a gate system would be NOR or NAND or JK or SR or master-slave or one-shot. The function it is performing, whether it is a shift-register, or line driver, or counter, power driver, etc. Type of logic and function must be compatible to maintain harmony in operation.

But many time trisect compatriot of prosperities may not result in selection of an ideal system. Say. tempted by the above factor, one may select an IC manufactured by some unknown company. Here lies the overall quality and reliability of that company in the future long run in the global market. Also, some of the manufacturer may discontinue their batch after some time, which may lead to serious design changes at the last phase of production time, a risky and cumber some job, indeed.

So, selection of a chip which is available in the market for a long time is a necessary requirement, which has ultimately debugged from production failures. Large amount of supply should be ensured. Technical assistance from the manufacturer should be obtained. The chip should be cost effective, i.e., cheaper. Also, should be cheaper in future. There are alternate manufacturers (compatible) and readily available. The product can work in diversified conditions, i.e., interfacing condition should be easy. These are few criteria one should keep in mind for selecting chip for their manufacturing process.

Now, comes the final testing of component inside the logic systems; its effect in the family, which includes fan-in, speed, propagation delay, type of gate, fan-out, etc.

Some may prescribe, a highly speed integrated logic circuit with propagation delay less than 1 neno-second and minimum cascading (minimum length for interconnecting path). Due to lead inductance and stray capacitance, longer signal path also creates cross-talk and ultimately cost of longer PCBs are always higher than simple PCBs.

In fact, nowadays logic circuits are selected in respect of their number of connection and length of interconnection rather than logic gates, which ultimately led to the idea of using Large-Scale-Intc-grated-Circuits (LSIC) and manufacturers are producing more complex logic circuits, namely micro computer systems, for example, a complete micro computer system on a single monolithic substrate.

Hence, by using LSICs physical size and length of interconnecting paths are drastically reduced, thus improving system efficiency at a very good rate. These leads to reduction of uses of conventional logic gates like, NOR/NAND, etc., a combination of them is always preferred.

Recently, even dependency on MSI and LSI components are reducing rapidly after introduction of VLSI (Very Large Scale Integration). However, MSI and LSI are used in some full-adders, shift registers, ROMs, PLAs, etc., using bipolar technology based on June tion transistor theory and MOS technology based on field effect transistor theory.

Using bipolar technology, speed of operation is being increased with almost no interference problem. But, this type of technology can not be used in larger chain, for example, more than 30 to 40 gates per square millimeter can create severe problem, i.e., the packing density should be kept low and hence this results in costly assembly.

To overcome this problem, a new type of bipolar technology has been introduced, known as integrated injection logic (PL), which gives almost similar speed and larger packing density, like CMOS devices (100-200+gates/sq. mm.). Microcomputer chips are using MOS and I2L technologies for LSICs.

On other hand, pin-limitation is a major constraint in LSI circuit design, where number of external connections is controlled by the physical size of the chip. DIL packages are usually found to be of 14, 16,24 pins and at most 64 pins. So, it is always important to obtain as much logic possible onto a single chip, using serial connection or coding method, thus increasing the gate-to-pin ratio.

It should be noted that, LSI circuits are not yet utilizing their full capacity and computer system designers are working at abreast to generate new LSI circuits. Few restrictions remain there, such as a viable design philosophy seems unfamiliar after few months, etc.

So,  to implement a computer system design as LSI circuit, the design must be separated into suit able chip sized sub-systems and component’s  position  should  be known before masking and etch ing. Robots are being used for these type of works, but still actual mask cutting, preparation and production of masks are very time con suming and expensive process (a mask may cost not less than us dollar 20,000). Hence development costs only can be recovered by mass scale production.

(To be continued…….)

* Hakikur Rahman B.Sc. Engg. (BUET), ME (AUB) Director, ICMS.

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