Professor Farruk Ahmed

Following the lead of the large computer systems, distributed processing is being applied to microcomputers. The requirements for processing power are outstripping the ability of the central processor to provide all the computation, data transfer and control in the system. Intelligent controllers are being added to the system design to allow the control problem to be partitioned and each part to be executed in parallel with the others.

Parallel processing results in higher system performance and through put by freeing the CPU for other tasks. Also the intelligent controllers are often optimized in’ architecture or algorithm to execute its tasks in a faster, more efficient more cost-effective manner than the CPU was able to do. Distributed architectures also allow the problem to be developed in a modular fashion. This makes the hardware and software design to be simpler and more easily maintained and upgraded.

Definition of a special purpose processor:

Special purpose processors (SPP) handle many of the same functions that the microcomputer peripheral chips perform. However, the SPP is distinguished by having an specialized instruction set to direct its functions independently of, but concurrently with, the CPU rather than the peripheral chip’s software controlled registers which need the direct control of CPU. There are other characteristics which may be employed to describe the various types of SPP. These are the characteristics which may be used to optimize the SPP to its task and its relationship to the host CPU.

There are two general forms of optimization: architectural and algorithmic. Architectural optimization is used for a single particular application that may require high performance (e.g., numerical computation, data communication, etc.). Algorithmic optimization uses a more general architecture to allow the design to be customized to the system needs. Here flexibility rather than performance is important.

The SPP can be run as a slave or a peer with respect to the host processor. The master slave system is a more understandable and conventional relationship. The slave deals with the real-time front end tasks, leaving the CPU free to handle only the high-level tasks. The peer SPP operates at the same technical level as the host and can share the host CPU’s memory and a I/O resources. The mode of communication between the tasks in these shared resources can involve a very high bandwidth. The tighter the coupling between the SPP and the CPU the higher the possible data transfer rates. Tight coupling usually implies a close physical proximity and a parallel bus connection. Loose coupling means a restricted bandwidth and the involvement of a serial data connection over a much wider area. Different types of SPP may be mentioned as follows:

(a)   Coprocessors— architectural optimization for high performance computation and I/O;

(b)   Slave processors— algorithmic optimization for flexibility at a low cost;

(c)   Signal processors— a hybrid of both for high speed data analysis, transforms, and correlations.


Coprocessors are of the form of architecturally optimized SPP. They are especially suitable for mathematically intensive and I/O intensive applications to improve the system perfoitnance while relieving the host CPU from doing these tasks. The internal architecture is not similar to a general CPU design, although it is complementary to the CPU’s architecture. Most of the coprocessors are actually dual processors: one section handles data and command while the other handles the I/O or mathematics.

The coprocessors are generally tightly coupled to the host CPU to support their high-performance operation. Mathematical coprocessors must be externally tightly coupled to the CPU as they are expected to act as an architectural extension of the host CPU. But the I/O control coprocessors are able to act independently of the CPU., operating on their own data and commands. These coprocessors can operate either on the CPU’s local bus or on a remote bus connected to the CPU through isolating buffers.

The first architectural extension coprocessor was Intel’s 8087 Numeric Processor Extension (NPX). The 8087 adds high-performance integer and floating point mathematics to the 8086 family of microprocessors. Other available numerical processor include the 8070 for Zilog’s Z 8000 and Z 80000, the 68881 for Motorola’s 68000 etc. In effect 8087 adds 69 new instructions and another eight 80-bit data registers to the host processor. It can execute single-precision multipliers 50 times faster than software routines. The 8087 needs no extra logic to be connected into an 8086 system. The 8067 can perform the processing of varied nature such as business data processing, robotic control etc. The Intel 80287 is the 8087′s counter part, is the numerical data processor for the 80286. The 80287 is upward software compatible with the 8087.

Peripheral Support Coprocessing:

Peripheral support coprocessors were developed to expand the I/O processing capabilities of the microprocessor system, reducing the load on the CPU at the same time. These devices may have built-in DMA capability, to speed data transfers and to have high processing power without CPU intervention. They are especially suitable in applications where intensive I/O data communication is involved. They behave very much like a regular processor in the sense they have independent instruction set and data structure. They may be of two types: dedicated support peripheral and general I/O processors.

Intel 82586 LAN controller, the 82730 Text coprocessor CRT controller are well known examples of dedicated type. Each of them have optimized architecture dedicated instruction set and data structures. The 8089 I/O processor (IOP) is an well-known example of general peripheral support I/O processor. The 8089 has two independent channels, each with its own register set and system control signals can execute its own program.

Slave Processors:

Slave Processors are at the other end of the SPP spectrum. They are lower-performance processors based on general purpose architectures and targeted at broad range of applications. The slave processor is always operated in a master-slave relationship to the host CPU. The slave processors are designed to do the front-end real-time work for the host CPU. The host does the high-level operations, and communicates with the slave through commands and data massages. The physical interface between the slave processor and the host CPU is always through the registers and or RAM built into the slave. Apart from data, status and control flag information are also provided. Provisions for DMA requests signal are sometimes included.

The master slave relationship with the host CPU, certainly, makes the system design to be flexible. There is no memory or I /0 resources to be shared, so the slave processor maybe connected locally or remotely to the host CPU. Another DMA device can handle the slave processor for the host. In all these cases the nature of coupling between the slave and the host processor is fairly tight.

Signal Processors:

The final type of SPP is the signal processor. These are especially designed processors characterized by high efficiency, complex arithmetic calculations. Signal processors are able to convert data from one format to another format, look for patterns within the data and isolate the particular data from the whole. The speed of operation is mostly high to cope with real-time data processing operations. In order to make the processer faster, the architecture and the algorithm are optimized. It may have on board memory, general purpose ALU and suitable instruction set. The data and instruction may be fetched in parallel without interference. The data paths are often split into parallel buses.

Signal processors may use hardware where general processors use software. The ALU widths up to 32 bits may be needed to maintain the high accuracy of the signal processing calculations. The Intel 2920 is the commonest example of signal processors. It contains four on boards 9 bit A/D and D/A converters.

The Future for SPP:

Development of special purpose processors will continue in all the types. In coprocessors new mathematical processors will become faster if more hardware can be dedicated to the problem. Communications, especially LANS, form the fast-growing field. Slave processors will continue to be developed especially to provide control functions not available elsewhere. The most flourishing field will be the signal processors. The fields of robotics and speech synthesis call for rapid development of signal processors. Speech recognition will be the next step on this path.

The development will, certainly, continue to provide answer to the never ending effort for accomplishing perfect system performance. It is to be borne in mind that a single processor cannot provide that needed performance. The time has now come, to accept the fact that a distributed multiprocessor system can only provide the required system performance.

* Dr. Faruk Ahmed

Chairman, Dept. of Applied

Physics & Electronics,

University of Dhaka

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